As a method for distributing a clock signal having a different frequency to each of a plurality of circuits (functional blocks) integrated in one semiconductor device, a method in which the frequency of a clock signal having a certain frequency is divided to generate clock signals having lower frequencies for respective functional blocks and the generated clock signals are distributed to the respective functional blocks has been proposed.
In a clock frequency divider circuit that divides the frequency of a clock signal to generate a clock signal having a lower frequency, it is easy to realize a divider circuit whose frequency division ratio, i.e., the ratio of the frequency of the generated clock signal to the frequency of the original clock signal is expressed as “1/M” (M is integer) (integer frequency divider circuit) by using a counter circuit.
Further, divider circuits capable of performing a frequency division even when the frequency division ratio is expressed as “N/M” (N and M are integers) (rational-number frequency divider circuit) have been also proposed (for example, Patent literatures 1 and 2). According to these related-art techniques, firstly, the value of the numerator of the frequency division ratio (the value of N in the frequency division ratio N/M) is cumulatively added at each cycle of the input clock signal. Next, if the addition result becomes larger than the value of the denominator of the frequency division ratio (the value of M in the frequency division ratio N/M), M is subtracted from the cumulative addition result. By performing these operations, and then appropriately masking (thinning out) clock pulses of the input clock signal by referring to the cumulative addition result, the related-art technique realizes a rational-number frequency division.
Further, as semiconductor devices become increasingly larger in scale and their operating frequencies become increasingly faster, the relative phase deviation between clock signals distributed in the semiconductor device, i.e., the so-called “clock skew” has been becoming a serious problem. If the clock skew becomes larger, the upper limit of the operating frequency of synchronous circuits is restricted, thus causing deterioration in performance.
As a technique to reduce the clock skew, clock tree circuits have been known in which clock buffers and clock wiring lines are arranged in a tree-like configuration. In this clock tree circuit, a clock buffer(s) are used at each level of the clock tree. Further, by designing the layout so that load capacities and wiring resistances become equal to each other, the delays that are caused in clock propagation paths extending from the input end of the clock tree to the respective output ends can be made equal to each other. As a result, it is expected that the phase differences between the clock signals occurring at the respective output ends become relatively smaller, and the clock skew is thereby reduced.
Specific examples of problems that occur in the above-described clock frequency divider circuit and the clock distribution circuit in the related art are explained with reference to FIGS. 8 and 9.
FIG. 8 shows an example of a semiconductor integrated circuit including circuits Ai (i is integer and 1≦i≦64) operating by clocks Ai (i is integer and 1≦i≦64), a communication circuit N operating by a clock N, a clock tree circuit 20, and a plurality of clock frequency divider circuits 100. The circuits Ai are connected to the communication circuit N, and communicate with each other through the communication circuit N. Each of the clock frequency divider circuits 100 is connected to one of the output ends of the clock tree circuit 20, thus forming a clock distribution circuit composed of the clock tree circuit 20 and the plurality of clock frequency divider circuits 100.
The clock tree circuit 20 uses a clock buffer(s) 22 at each level of the clock tree, and its layout is designed so that load capacities and wiring resistances become equal to each other. In this way, the clock skew of the clock S and the clocks Ai is reduced. Further, the clock N is also distributed by using a clock tree circuit (not shown) so that the distribution delays of the clock N and the clock S become equal to each other. In this way, the clock skew of the clock N, clock S, and clocks Ai is reduced, thus enabling the circuits Ai and the communication circuit N to communicate with each other in a synchronized manner.
The clock frequency divider circuits 100 in the related art generate the clocks Ai by performing a rational-number frequency division on the clock S, which is distributed by the clock tree circuit 20, based on input frequency division ratio setting.
The clock frequency divider circuits 100 in the related art realize a frequency division by selectively masking clock pulses of the input clock signals. However, this related-art technique does not give any consideration to the communication with the communication circuit N operating by a clock having a different frequency. Therefore, there is a problem that the communication with the communication circuit N requires a special clock transfer circuit and/or special timing design. In addition, there is another problem that the communication performance deteriorates because of the above-described problem. Further, there is another problem that when the frequency division ratio is changed, it is necessary to change the communication timing with the communication circuit N according to that change.
FIG. 9 is a diming diagram showing an example of a clock frequency division performed by a clock frequency divider circuit 100 in the related art. The figure shows clocks Ai generated by dividing the frequency of the clock S at frequency division ratios 11/12 to 4/12. The clocks Ai can be generated by appropriately masking clock pulses of the input clock S. For example, a clock Ai corresponding to the frequency division ratio 9/12 is generated by masking three clock pulses at timings T3, T8 and T11 among the twelve clock pulses at the timings T0 to T11 of the clock S.
In this example, assume that the frequency of the clock N is one third of that of the clock S. That is, the frequency division ratio of the clock N to the clock S is 1/3 (=4/12). Note that the phase relation between the clock N and the clocks Ai makes a full circle in twelve cycles of the clock S. The timings of the twelve cycles, in which the phase relation makes a full circle, are represented by “T0” to “T11”.
Assume also that the circuits Ai and the communication circuit N communicate with each other at the timings T0, T3, T6 and T9, which correspond to all the rising edge timings of the clock N. In particular, at the timings T0, T3, T6 and T9, the circuits Ai output a signal to the communication circuit N and/or receive a signal sent from the communication circuit N. Similarly, at the timings T0, T3, T6 and T9, the communication circuit N outputs a signal to the circuits Ai and/or receives a signal sent from the circuits Ai.
However, the clock frequency divider circuit 100 in the related art does not give any consideration to the communication with a circuit operating by a clock having a different frequency. Therefore, there are cases where a clock pulse of the clock S is masked even at this communication timing to generate a certain clock Ai.
In the example shown in FIG. 9, some of the clock pulses are masked at the timings T3, T6 and T9 among the communication timings to generate the clocks Ai. Specifically, at the timing T3, the clock pulse is masked for the frequency division ratios 9/12 (110a), 6/12 (110b), and 5/12 (110c). Similarly, at the timing T6, the clock pulse is masked for the frequency division ratio 5/12 (110d). Similarly, at the timing T9, the clock pulse is masked for the frequency division ratios 7/12 (110e), 6/12 (110f), and 5/12 (110g).
If the clock pulse of the clock S is masked at the communication timing to generate a clock Ai as in the case of the above-described example, a circuit Ai operating by the generated clock Ai cannot receive a signal output from the communication circuit N operating by the clock N at an expected timing. Similarly, the circuit Ai operating by the clock Ai cannot output a signal at the timing that is expected by the communication circuit N operating by the clock N.
Therefore, in the clock frequency divider circuit in the related art, there is a problem that the communication with a circuit operating by a clock having a different frequency requires a special clock transfer circuit and/or special timing design to realize an expected proper communication operation. As a result, there is another problem that the communication performance deteriorates. Further, there is another problem that when the frequency division ratio is changed, it is necessary to change the timing of communication with the circuit operating by a clock having a different frequency according to that change.
Furthermore, in the clock distribution circuit shown in FIG. 8 in which each of the clock frequency divider circuits 100 is connected to one of the output ends of the clock tree circuit 20, the clock S, which is distributed by the clock tree circuit 20, always has a high frequency because its frequency is not divided. Therefore, there is another problem that the power consumption of the clock tree circuit 20 is large.